Build Xyce from Source for ADMS Verilog-A Model Integration

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Knowm Memristor Array

Xyce is a new (relative to the original SPICE) circuit simulator from Sandia National Laboratories that is SPICE-compatible but operates in a fundamentally different way under the hood. Xyce boasts a modern code base, an active forum, supports large-scale parallel computing architectures to accelerate simulations and it’s open source too! We have recently adopted Xyce in order to further develop several memristor models including our own The Generalized Metastable Switch Memristor Model, as Xyce is able to integrate Verilog-A models into Xyce-compatible C++ code using the ADMS model compiler with the Xyce/ADMS back-end. In this blog post I demonstrate how to build Xyce from source so that it is able to do the Verilog-A model integration via the plug-in mechanism. I am using Xyce 6.6, MacOS Sierra, Trilinos-12.6.4, Homebrew and gcc6. Other systems such as Linux and Windows would need to slightly modify these instructions, but the basic idea should be very similar.

Install Xyce the Easy Way

It is possible to install a Xyce binary forgoing the process of building it yourself. You won’t be able to integrate Verilog-A models into Xyce though. Compiled binaries of Xyce for most platforms can be found at https://xyce.sandia.gov/downloads/Binaries.html.

Install Xyce the Hard Way – Build from Source

First download the source (requires registration).

Dependencies with Homebrew

Required for running regression test scripts (see below)

Required for building Xyce and Dependencies

ADMS – An Automatic Device Model Synthesizer

ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile C code for the API of SPICE simulators. Based on transformations specified in XML language, ADMS transforms Verilog-AMS code into other target languages.

Building ADMS with Autotools will require some further Perl modules

Install into system-wide Perl

Let’s assume we have a directory for installing all the EDA tools called ~/workspaces/workspace_eda.

Xyce ( Serial ) Build Instructions

Xyce Dependencies – Trilinos-12.6.4 ( Serial )

Setup out of source build directory ( Serial )

Create a config script

Save script and change mode to executable

Configure, Build and Install ( output creates ~/workspaces/workspace_eda/XyceLibs/Serial )

Download the 3 Xyce_6.6 tarballs from Sandia National Labs and copy to ~/workspaces/workspace_eda

Extract the folders

Build Xyce ( Serial ) with advanced features using XyceLibs ( Serial )

Setup an out of source build directory

Create a config script

Here we take the script given on the Xyce building guide and modify it to our system and preferences. We add ADMS_CXXFLAGS="-O1" to reduce the optimization of the ADMS components which will vastly improve compile times. We also add --disable-adms_sensitivities to turn off analytic sensitivity derivative calculation for Verilog-A-derived devices. These and more optimization tips can be found on the build guide in section Special note for building on small-memory computer systems. You must configure Xyce using the --enable-shared and --enable-xyce-shareable option in order to integrate your own Verilog-A/ADMS models.

Save script and change mode to executable

Configure and build

Lets’ first check how many cores we have (MacOS):

Use the -j option to define the number of cores compiling should use, in this case 4.

If you get permissions errors in ~/workspaces/workspace_eda/Xyce-6.6/build/serial/src when trying to recompile, run:

For me it was:

Run regression tests before installing

Create a config script

Save script and change mode to executable

Run tests ( NOTE: A few tests may fail depending on the availability of some features and prerequisites )

Install Xyce ( Serial ) outputs Xyce binary & buildxyceplugin to /usr/local/bin

Read the Xyce User Guide and start simulating!

Xyce ( Parallel ) Build Instructions

Building Trilinos for use in Parallel Xyce requires enabling some additional Trilinos packages (Zoltan and ShyLU) and enabling ParMETIS library support. It also requires using the compiler wrappers provided by your system’s MPI package (ex. Open MPI) instead of the compilers (gcc, g++, gfortran) directly. These wrappers are typically called “mpicc,” “mpic++”, and “mpif77”, but your system may install them with different names or special paths.

To build for parallel, follow the instructions here, making slight modifications to the above instructions. You can use a diff tools to see the differences that need to be applied.

Additional Xyce Dependencies with Parallel support

Example Circuit for Testing

This is taken from the user manual linked to above.

Xyce will run the simulation and create a .prn file. Xyce does not have it’s own graphical system for displaying results and a third party tool is necessary. They recommend gnuplot and Tecplot. To get a quick and dirty plot with the software I already had installed, I changed the .prn file to a .csv file and imported it into Libreoffice.

Xyce Hello World CSV

Xyce Hello World Tran

Joglekar Resistance Switch Memristor Model

Having previously simulated a memristor in LTSpice using the Joglekar nonlinear drift window function, we adapt that netlist to the required syntax of Xyce.

The following code can be found on the memristor-models-4-all project.

Note that we added the option FORMAT=CSV to directly get a CSV file as output so we don’t have to manually change the file extension before importing it into LibreOffice. Following is the familiar pinched hysteresis loop response of the memristor in response to a sinusoidal input.

Xyce Memristor I-V

Plotting with GNUPlot

The official Xyce manual states that GNUPlot is a popular choice for plotting the results of a simulation. As using LibreOffice is quite slow and cumbersome and GNUPlot could be wrapped into a script, we show how to do that next. Since I’m using a Mac, gnuplot is installed easily with homebrew:

To make the plot, run the following code making sure you removed the FORMAT=CSV from the original simulation file and running it again to create the .prn file.

Xyce GNUPlot Memristor

Schematic Capture

For a decent tutorial on how to build a netlist automatically from a schematic capture tools and to plot the results using gnuplot see: Using Open Source Schematic Capture Tools With Xyce.

According to the Xyce Reference Guide page 484, Xyce has the Yakopcic and TEAM models integrated natively. The source code for these files is in .../workspaces/workspace_eda/Xyce-6.6/src/DeviceModelPKG/OpenModels/src/N_DEV_MemristorYakopcic.C and .../workspaces/workspace_eda/Xyce-6.6/src/DeviceModelPKG/OpenModels/src/N_DEV_MemristorTEAM.C

Custom Verilog-A Device models for Xyce

The rest of this blog covers the steps in integrating a simple test Verilog-A model, which comes with the Xyce source code, into a Xyce simulation. Xyce does not at this time have any capability for direct import of Verilog-A models through a netlist. Before a model written in Verilog-A can be used, it must be converted to C++ using Xyce/ADMS, compiled, and linked into Xyce. The plugin method requires that Xyce be built specially to support shared library loads — the standard binary distributions of Xyce do not support this feature yet. A script is provided with Xyce that simplifies the generation and installation of such plugins, and a command-line option is available to load the plugin at run time.

Because we previously used the compiler flags --enable-shared and --enable-xyce-shareable in order to integrate your own Verilog-A/ADMS models, we should have a utility in usr/local/bin called buildxyceplugin. What this utility will do is compile your Verilog-A model files and simulation circuits using these models into a system library file with a *.so extension in usr/local/lib. Then when you run Xyce, you just need to tell it about this library with the -plugin option and then use Xyce like normal. Let’s build the Verilog-A examples that came with Xyce to make sure everything is working before building our own models.

First, we copy the toys directory form the Xyce source code to a different place. This way we won’t accidentally change anything important in Xyce’s source tree and mess up a future compile. We can do whatever we want with it. In this case, I copied Xyce-6.6/utils/ADMS/examples/toys to ~/Desktop.

Navigate to the directory containing the Verilog source

Build a plugin

Test the plugin

Plot the results

Xyce Verilog Diodeclipper

Xyce Links

• What is Xyce?
• Xyce Website: http://xyce.sandia.gov/
• Main Repository (requires registration): https://xyce.sandia.gov/downloads/sign-in.html
• Mirror Repository: https://xyce.sandia.gov/downloads/source_code.html
• 3rd Party Libraries: https://xyce.sandia.gov/downloads/3rd_party_libraries.html
• Forum: https://groups.google.com/forum/#!forum/xyce-users
• Source code documentation:
  • Docs – https://xyce.sandia.gov/documentation/index.html
  • FAQ – https://xyce.sandia.gov/documentation/FAQ.html
  • Building Guide – https://xyce.sandia.gov/documentation/BuildingGuide.html
• Xyce User Guide

Verilog-A Links

1. Verilog-A on Wikipedia
2. Writing your first Verilog-A compact model
3. Introduction to Verilog-A
4. Verilog AMS Manual

Further Resources

• Knowm Memristors
• The Generalized Metastable Switch Memristor Model
• The Problem is Not HP’s Memristor–It’s How They Want To Use It
• The Joglekar Resistance Switch Memristor Model in LTSpice
• memristor-models-4-all Project on Github
• The Pershin Voltage Threshold Memristor Model in NGSpice
• Well-posed Memristor Modeling with Xyce and Verilog-A