Knowm Memristors

In addition to our original Tungsten Knowm memristor we’re happy to announce the availability of three new variations of probe-able raw die – Chromium, Tin and Tungsten – each containing 180 individual memristors in 9 different device sizes. To round out our memristor offerings, we are now making raw device data available for purchase, mainly intended for researchers who may not have the necessary equipment for characterizing memristors. While these memristors were designed for our own neuromemristive processor, Thermodynamic RAM, they are also excellent candidates for other memristor applications such as non-volatile RAM, oscillators, analog computing, ternary arithmetic and logic.

We are the first to develop and make commercially-available memristors with bi-directional incremental learning capability. The device was developed through research from Boise State University’s Dr. Kris Campbell, and this new data unequivocally confirms Knowm’s memristors are capable of bi-directional incremental learning. This has been previously deemed impossible in filamentary devices by Knowm’s competitors, including IBM, despite significant investment in materials, research and development. With this advancement, Knowm delivers the first commercial memristors that can adjust resistance in incremental steps in both direction rather than only one direction with an all-or-nothing ‘erase’. This advancement opens the gateway to extremely efficient and powerful machine learning and artificial intelligence applications.

The Knowm Memristor devices operate primarily through the mechanism of electric field induced generation and movement of metal ions through a multilayer chalcogenide material stack. A secondary mechanism of operation is phase-change, which can be selected as the primary mode of operation depending upon the operating conditions. Read More The Knowm Memristors come in three variants: W, Sn and Cr, which refers to the metal introduced in the active layer during fabrication. Each device is available in both raw die and packaged devices.

Knowm W, Cr, and Sn Memristor Types

In the following video, Alex Nugent, explains what a memristor is, some facts and misconceptions and introduces Knowm Inc.’s commercially available memristors.

16 Pin DIP Format

The material stack is based on mobile metal ion conduction through a chalcogenide material. The devices are fabricated with a layer of metal that is easily oxidizable, located near one electrode. When a voltage is applied across the device with the more positive potential on the electrode near this metal layer, the metal is oxidized to form ions. Once formed, the ions move through the device towards the lower potential electrode. The ions move through a layer of amorphous chalcogenide material (the active layer) to reach the lower potential electrode where they are reduced to their metallic form and eventually form a conductive pathway between both electrodes that spans the active material layer, lowering the device resistance. Reversing the direction of the applied potential causes the conductive channel to dissolve and the device resistance to increase. The devices are bipolar, cycling between high and low resistance values by switching the polarity of the applied potential. The resistance is related at any time to the amount of metal located within the active layer.

Knowm Memristors

Eight (8) discrete memristors in 16 Pin Ceramic DIP (Dual Inline Package) with wafer batch and serial number. They are available for research and development at the following URL: knowm.org/product/bs-af-w-memristors.

Raw Research Die

The research die were created to allow study of device operation over a wide range of device sizes. The die are 7860 μm by 5760 μm and consists of 9 columns of devices, each corresponding to a different device size. The size is listed at the bottom of each column. Each column contains 20 rows of each device size per column, for a total of 180 devices. The row number is listed at the left of each row. The top row, not numbered, is a metal continuity row that is used as a diagnostic tool for checking probe station functionality. There are no devices in this row. Instead the row consists of two shorted top electrode bond pads and two shorted bottom electrode bond pads above each column. Note that the outer ring around the die shows the alignment structures for the photolithography mask layers used during fabrication.

Knowm Memristors

The top and bottom electrodes for each device are denoted by the purple and blue squares, respectively. The top row in the die, not numbered, consists only of metal continuity structures: two bond pads corresponding to the top electrode shorted together, and two bond pads corresponding to the bottom electrode shorted together. These structures are used to check probe station functionality.

An optical image of a section of the research die (taken through a microscope) is shown below. Two devices are shown in the image. The device via and the top and bottom electrodes are annotated.

Raw Die Close Up

The device via confines the device material between the top and bottom electrodes and defines the size of the device. The device via is located at the intersection of the top and bottom electrodes. This is the region where the top electrode metal and bottom electrode metal intersect. The device sizes included in the research die are 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 10μm, 20μm, and 30μm and refer to the dimension of the device via. For devices of size 6 μm or less, the device via is round and the size refers to the nominal via diameter. For devices of sizes 10 μm, 20 μm, and 30 μm, the device via shape is square and the size corresponds to the nominal length of a side.

There are three different memristor material types available in the research die:

1. GeSeW (the ‘W’ device)
2. GeSeSn (the ‘Sn’ device)
3. GeSeCr (the ‘Cr’ device)

Each memristor type has the same basic material structure, but they differ in the active metal added to the chalcogenide active layer.

Characteristic Value
Die Width 7860 μm
Die Height 5760 μm
Device Sizes (Quantity) 1 μm(20), 2 μm(20), 3 μm(20), 4 μm(20), 5 μm(20), 6 μm(20), 10 μm(20), 20 μm(20), 30 μm(20)
Total Devices per Die 180

Handling

The preferred method of handling the die is by hand or with an air wand or other soft contact method. If you use tweezers, touch only the sides of the die, not the top surface as you will likely damage devices. Wear gloves when touching the die by hand.

The devices are static sensitive and not protected. use the proper ESD protection when handling the die.

Device Probing

A micro-probe station is recommended for hand-probing die. An example micro-probe station is shown below. Commonly used micromanipulator probe tip is a Micromanipulator 7A or 7B tungsten probe tip, or the equivalent.

Probe Station

DC Electrical Characteristics of the Raw Die Devices

Note: These results are unique to the initial forming method and entire history of the device leading up to the data collection. Different forming procedures and histories will result in different characteristics. Shown below are some DC response statisics from the raw die devices after the following forming procedure was used. Also note that the packaged memristor devices cannot be exactly represented by these statistics, as they were made during a different wafer run and the packaging and internal wire bonding contributing to different bahavior.

For the Cr wafer, the forming procedure is:
1) Apply a sinewave with 0.6 V peak amplitude, 100 Hz, for 20 cycles to condition the devices.
2) Apply a read – erase – read pulse sequence with the read pulses 500 ns width, and the amplitude of 200 mV; the erase pulse is 5 µs width, -1.5 V amplitude.
3) Apply three consecutive cycles of R-W-R-E with all pulse widths 1 µs, write amplitude 900 mV, erase amplitude -1.2 V and read amplitudes of 200 mV.
4) Apply a R-Wx20-R sequence with a reduced write amplitude (700 mV, 1 µs pulsewidth).
5) Apply a R-Ex20-R with -1V, 1usec amplitude.
6) Repeat 4.
7) Repeat 5.

DC Response

Cr (Chromium) Raw Die

Characteristic Condition Min Typ Max Std
Forward Adaptation Threshold DC / quasi-static 0.220 V 0.332 V 0.560 V 0.089 V
Reverse Adaptation Threshold DC / quasi-static -0.660 V -0.189 V -0.040 V 0.154 V
Cycle Endurance 1.5 Vpp, 500 Hz sine wave, 50 kΩ Series resistor 1M 50M 100M
Low Resistance State 100nA Write Compliance Current 5.48E6 Ω 2.62E7 Ω 4.33E7 Ω 1.25E7 Ω
High Resistance State 100nA Write Compliance Current 1.07E11 Ω 1.59E12 Ω 9.00E12 Ω 2.62E12 Ω
Low Resistance State 1uA Write Compliance Current 1.51E5 Ω 1.90E6 Ω 1.04E7 Ω 2.87E6 Ω
High Resistance State 1uA Write Compliance Current 7.41E7 Ω 1.88E11 Ω 7.63E11 Ω 2.51E11 Ω
Low Resistance State 10uA Write Compliance Current 3.29E4 Ω 5.67E4 Ω 9.90E4 Ω 2.23E4 Ω
High Resistance State 10uA Write Compliance Current 2.53E7 Ω 1.14E11 Ω 1.00E12 Ω 2.96E11 Ω
Low Resistance State 100uA Write Compliance Current 2.65E3 Ω 4.82E3 Ω 1.05E4 Ω 2.09E3 Ω
High Resistance State 100uA Write Compliance Current 3.40E5 Ω 9.54E6 Ω 6.17E7 Ω 1.80E7 Ω
Low Resistance State 1mA Write Compliance Current 3.86E2 Ω 6.63E2 Ω 9.59E2 Ω 1.81E2 Ω
High Resistance State 1mA Write Compliance Current 3.63E4 Ω 7.49E4 Ω 1.49E5 Ω 4.04E4 Ω

Sn (Tin) Raw Die

Characteristic Condition Min Typ Max Std
Forward Adaptation Threshold DC / quasi-static 0.150 V 0.259 V 0.340 V 0.042 V
Reverse Adaptation Threshold DC / quasi-static -0.230 V -0.094 V -0.030 V 0.053 V
Cycle Endurance 1.5 Vpp, 500 Hz sine wave, 50 kΩ Series resistor 50M 100M 5B
Low Resistance State 100nA Write Compliance Current 7.41E5 Ω 7.17E6 Ω 3.56E7 Ω 9.87E6 Ω
High Resistance State 100nA Write Compliance Current 1.64E9 Ω 9.81E11 Ω 8.00E12 Ω 2.35E12 Ω
Low Resistance State 1uA Write Compliance Current 2.50E5 Ω 1.58E7 Ω 3.79E7 Ω 1.53E7 Ω
High Resistance State 1uA Write Compliance Current 7.60E6 Ω 2.23E11 Ω 1.43E12 Ω 4.10E11 Ω
Low Resistance State 10uA Write Compliance Current 3.14E4 Ω 1.57E5 Ω 1.16E6 Ω 3.33E5 Ω
High Resistance State 10uA Write Compliance Current 3.26E6 Ω 5.21E10 Ω 3.16E11 Ω 1.04E11 Ω
Low Resistance State 100uA Write Compliance Current 1.75E3 Ω 4.62E3 Ω 1.05E4 Ω 2.90E3 Ω
High Resistance State 100uA Write Compliance Current 5.64E5 Ω 5.80E10 Ω 2.50E11 Ω 8.22E10 Ω
Low Resistance State 1mA Write Compliance Current 2.58E2 Ω 3.04E2 Ω 3.44E2 Ω 2.67E1 Ω
High Resistance State 1mA Write Compliance Current 2.02E4 Ω 9.08E4 Ω 2.97E5 Ω 7.89E4 Ω

W (Tungsten) Raw Die

Characteristic Condition Min Typ Max Std
Forward Adaptation Threshold DC / quasi-static 0.150 V 0.258 V 0.350 V 0.049 V
Reverse Adaptation Threshold DC / quasi-static -0.270 V -0.108 V -0.050 V 0.057 V
Cycle Endurance 1.5 Vpp, 500 Hz sine wave, 50 kΩ Series resistor 50M 100M 5B
Low Resistance State 100nA Write Compliance Current 1.04E6 Ω 1.38E6 Ω 2.16E6 Ω 3.01E5 Ω
High Resistance State 100nA Write Compliance Current 4.01E6 Ω 8.17E6 Ω 1.72E7 Ω 3.77E6 Ω
Low Resistance State 1uA Write Compliance Current 1.50E5 Ω 4.67E5 Ω 1.30E6 Ω 3.09E5 Ω
High Resistance State 1uA Write Compliance Current 5.39E6 Ω 1.40E7 Ω 5.40E7 Ω 1.40E7 Ω
Low Resistance State 10uA Write Compliance Current 2.66E4 Ω 6.74E4 Ω 1.72E5 Ω 4.62E4 Ω
High Resistance State 10uA Write Compliance Current 2.36E6 Ω 9.19E6 Ω 2.04E7 Ω 5.70E6 Ω
Low Resistance State 100uA Write Compliance Current 1.93E3 Ω 7.86E3 Ω 4.63E4 Ω 1.30E4 Ω
High Resistance State 100uA Write Compliance Current 1.99E5 Ω 2.71E6 Ω 1.60E7 Ω 4.70E6 Ω
Low Resistance State 1mA Write Compliance Current 2.65E2 Ω 2.94E2 Ω 3.53E2 Ω 2.44E1 Ω
High Resistance State 1mA Write Compliance Current 1.50E4 Ω 5.60E4 Ω 1.13E5 Ω 2.84E4 Ω

Note:

1. Higher potentials can lead to phase-change operation. See Warnings section.
2. High and low resistance states were measured from a DC erase sweep following a DC write sweep set to the stated compliance current.
3. We currently have limited data on cycling endurace. Higher voltages will reduce device lifespace.

Warnings

Static Sensitive

Devices are sensitive to electrostatic discharge. Please use accepted methods for handling static-sensitive devices including anti-static packaging, work-surfaces, wrist straps, etc. Do not touch the package leads without taking precautions against electrostatic discharge. Devices will be irreversibly damaged if these precautions are not observed.

Do not measure resistance with a multi-meter

Due to high open-circuit voltages, multi-meters will damage the devices.

Limit Device Current

Set a compliance current or use series resistance. A forward applied voltage will cause devices to enter a very low-resistance state and consequently burn out.

Limit Applied Voltage

Formed devices typically change resistance between 0.1 and 0.75 Volts and are intended to be normally operated under 1 V. High voltages may induce (reversible) phase-change or (non-reversible) damage.

Device Forming

The shipped raw die devices have not been formed. Packaged die may or may not have been completely formed when delivered, as only enough sinusoidal voltage was applied for quality control to make sure the internal wire bonding was successful or not. Forming entails applying a gradually increasing voltage, while limiting current, until the necessary conductive pathways have formed. There in no single correct way to form the devices, many different procedures will work, but may have different outcomes for device behavior.

Forming Method 1

Apply a sine wave input and gradually increase the amplitude of the sine wave until the device responds. To apply the sine wave to the device safely, build a circuit as shown below with the memristor in series with a current-limiting resistor greater than 1 kΩ. As shown in the following figure, use an oscilloscope to measure at points Px and Py and place oscilloscope into “xy” mode. Apply a 1 to 100 Hz sine wave with an amplitude of 0.25 V amplitude. Gradually increase the voltage until a hysteresis loop is visible. You may need to continue on with higher voltage depending on your current-limiting resistor to get the device to completely form even after the initial hysteresis loop appears. Decrease the voltage until the hysteresis loop disappears and then gradually increase the voltage again until a hysteresis loop re-appears. If the device had not previously been formed for you, the voltage at which the hysteresis loop reappears will be less than the voltage needed for forming.

Forming Method 2 Setup

An example of the type of waveform you can expect on Px and Py is shown in the figure below. Since the device is operating in ion-conduction mode only, the voltage across the load responds by following the input waveform during the positive cycle, and during the negative-going erase cycle until the erase threshold causes the device resistance to increase (the ‘spike’ in the negative portion of Py waveform).

Ion-Conduction Mode

Ion-conduction mode cycling. The Py waveform allows observation of the device response to the input. The positive portion of the input sine wave causes the device resistance to drop. The negative portion causes the device resistance to increase once the erase threshold is reached (shown by the ‘spike’ in the Py trace).

Watch online video here: https://vimeo.com/knowm/formingaknowmbs-af-wmemristor

Forming Method 2

As presented above in the DC Electrical Characteristics of the Raw Die Devices section and copied below, the following precisely controlled forming procedure is the one we used for the raw die devices. You might come up with a similar procedure after testing various options and finding the best method. Note that this procedure may or may not be optimal for the packaged devices.

1) Apply a sine wave with 0.6 V peak amplitude, 100 Hz, for 20 cycles to condition the devices.
2) Apply a read – erase – read pulse sequence with the read pulses 500 ns width, and the amplitude of 200 mV; the erase pulse is 5 µs width, -1.5 V amplitude.
3) Apply three consecutive cycles of R-W-R-E with all pulse widths 1 µs, write amplitude 900 mV, erase amplitude -1.2 V and read amplitudes of 200 mV.
4) Apply a R-Wx20-R sequence with a reduced write amplitude (700 mV, 1 µs pulsewidth).
5) Apply a R-Ex20-R with -1V, 1 µs amplitude.
6) Repeat 4.
7) Repeat 5.

Phase-Change Response

The memristor device has two main modes of operation: ion-conducting and phase-change and it can be put into a state that consists of a combination of the two modes. The hysteresis and incremental response will vary depending on which mode the memristor is currently in.

Phase-change operation can only occur after the device has previously been operated at least once in the ion conduction mode because there is a permanent material change in the active layers that occurs upon ion conduction. To achieve phase change operation, the device is operated under higher voltage and current conditions. Typical phase-change device melt-quench operating procedures should be used to increase resistance when in this mode. Additionally, this mode allows single polarity operation, if desired. To get the device out of phase-change mode apply a short, higher voltage, melt and quench pulse.

The following figure is showing a phase-change response at the higher applied voltage on the erase side. The erase side is typically where these devices do that the easiest. Sometimes on the positive V side, you may see something that could be misinterpreted as the S-shape, but it is the ion motion and snap back due to formation of a conduction pathway via mass movement.

Phase Change Response

A word of caution when switching between phase-change and ion-conducting operational modes: the device can ‘switch’ polarity in the ion conducting mode when the operational mode goes from phase-change back to ion conduction. This means that the voltage polarities needed at the electrodes in order to increase the resistance are opposite from what they were initially. The ion conduction polarity switch occurs especially if the phase change operation applied a positive potential pulse to the device top electrode. In this case, the ion-conducting mode will operate as if the excess silver layer has moved towards the original bottom electrode. Application of pulses or a DC sweep to drive the silver back towards the top electrode will return the device to its original operating polarity.

Raw Memristor Device Data

Knowm Memristor device data covering the Cr, Sn and W devices over a range of testing conditions. Comma Separated Value (CSV) files directly exported from semiconductor device parameter analyzers covering AC, DC, and Pulse driving conditions. Data retention tests covering multiple initial starting resistances over sixty minutes. 1,016 Total Files, 197.4MB.

Sn, Cr and W Memristor Variants Including Raw Device Data Now Available!

This raw data is mainly intended for researchers who may not have the necessary equipment for characterizing memristors.

Symbology

This symbol is used internally at Knowm as it is easier to draw by hand and more accurately represents the definition of a memristor.

The bar signifies the electrode adjacent to the active chalcogenide layers. In the pristine device, this is the layer furthest away from the original Ag layer. While in ion-conduction mode, a voltage applied across the device with the lower-potential end on the side of the bar, will drive the device into a high conductance state.

Knowm Memristor Symbol

We believe the natural direction for conductance change in a memristor should defined as increasing, as this is how most adaptive dissipative systems in Nature evolve over time. By convention, a bar signifies the lower potential end in other devices like diodes. Furthermore, from an electro-chemistry merged with a semiconductor devices perspective, we believe having the bar on the cathode makes the most since this is where reduction occurs.

Dr. Kris Campbell at Boise State University

Device Inventor

Kris Campbell is both a scientist and an engineer, with a passion for creating and building new device technologies. She loves everything about chemistry and believes that a solid foundation in chemistry is one of the best things a student in any science or engineering discipline can give to themselves. With it comes an appreciation for all things in nature and in the science surrounding technology. As both a chemist and an electrical engineer, she has had a range of professional experiences from electro-optic circuit design, and nonvolatile memory device technology development and fabrication, to teaching. She is currently an Associate Professor in the electrical and computer engineering department at Boise State University. Kris Campbell has over 10 years of electrical engineering industry experience in the areas of microfabrication and optoelectronic circuit design. Kris has published over 20 papers in peer reviewed journals, 2 book chapters, and several conference proceedings. Her current research interests are in the areas of reconfigurable electronics based on ion-conducting chalcogenide glasses, and new electronic memory technologies based on ion-conduction and electron spin zero-field splitting.

University of California, Davis Physical Chemistry Ph.D.
University of Nevada, Las Vegas Electrical Engineering B.S.E.E.

The Trouble with Oxide-Based Memristors

By Kris Campbell

I have been asked a number of times how the memristors I designed for Knowm Inc. differ from HP’s memristor. For every comment I make, I have to stress that I have not personally tested HP’s memristors. Their actual electrical properties could deviate from my own experience fabricating similar devices and from what I’ve read and heard from others. The problem with relying on second-hand reports is that the electrical properties of a memristor can be significantly altered by how the device was previously tested or handled. I don’t know how sensitive HP’s devices are or how easily they can be damaged. Sometimes one can observe erratic behavior due to previous mishandling of the device, so without knowing the exact history you can never be 100% sure. Given the above, my observations from similar devices that I have fabricated are congruent with what others, who have tested HP’s memristors, also claim.

They have been described as erratic, with high switching voltages, high forming voltages, and non-repeatability from device-to-device. The published literature for HP’s devices claim it is comprised of a metal oxide material that relies on the migration of oxygen vacancies to alter the resistance of the device. This oxygen vacancy migration is related to the volume of the device active layer and is thus considered a ‘bulk’ migration, not necessarily a filament through the device.

However, that being said, there are also patents (by other companies researching metal-oxide resistive RAM) that support the development of a device structure using oxygen vacancies that form a filamentary conduction path or percolation path (e.g., US8648418, US9012881B2,US20130341584A1). I do not know if HP is implementing any of these types of designs, or even perhaps something new. Other types of metal-oxide devices are described in the patent literature to address the erratic switching issues, and the high forming voltages (US8062918B2, US20140054531A1, US8441838). Even more patents address molecular control of the oxygen vacancies through material design and device structure (e.g., US8420478B2). There are hundreds of patents that address these issues, and what I reference above can serve to get anyone that is really interested in digging deeper a starting point

From my own experience with some of the metal-oxide devices, such as HfOx, I have found that oxides are very difficult to design a stable device with. First, it is very difficult to control the concentration of oxygen within a film. Fabrication techniques become complicated every step of the way. Keeping oxygen out of the device after fabrication is also challenging. I have first hand observed device-to-device variation in metal oxide devices that I’ve fabricated, with high switching voltages, erratic behavior within the same device, and poor state retention.

My opinion is that it is difficult to fabricate devices with metal-oxides since it is difficult to control or regulate the concentration of oxygen in the device. This means that every time one tries to fabricate devices, they may get different results due to any small change in the way the wafers were processed. This is an exercise in frustration. Different film deposition methods will produce devices with drastically different electrical characteristics. I do not use oxides for this reason.

Benefits that I’ve heard attributed to oxide-based memristors include that they would be compatible with CMOS processing or that they can withstand higher temperatures during fabrication. I disagree with the compatibility analogy since the metals of the metal oxides may still pose a problem as a contaminant in a clean room, especially if the materials have been specially designed to address a particular problem. Compatibility can be addressed through circuit designs that place the memristor fabrication as a back-end-of-line (final) processing step. The higher processing temperatures could certainly be true, but through back-end-of-line processing, this isn’t an issue.

The Knowm memristor devices do not use oxygen vacancy migration to change the device resistance. The Knowm memristor uses layers of chalcogenide materials. Due to the amorphous nature of the materials–meaning they are disordered and not affected by impurities due to Fermi level pinning, they can take on impurities such as oxygen with little to no observable effect on the electrical properties. The devices rely on both a phase-change and a filamentary conduction mechanism, with the filamentary conduction mechanism dominating during “normal” low-voltage operation. The active layers do not have a need for precise thicknesses and they can be deposited in a variety of ways, including the simple technique of sputtering. Even with fabrication in the university clean room where pieces of equipment are in constant flux, even with unexperienced undergraduate students fabricating the devices, they still behave with similar electrical properties every time. The switching voltages are low, the forming voltage is low, device switching is consistent, and fabrication is simple.

CMOS+Memristor BEOL Service

Via Knowm’s collaboration with Boise State University, we offer the world’s first CMOS Back End Of Line (BEOL) Memristor service. We are offering this service to lower the barriers to memristive technology and help jump-start the memristor-based computing era. Multiple memristor types are possible covering a range of threshold voltages, resistance ranges, switching speeds, data retention, and cycling durability. Services includes layout design, all microfabrication steps for device fabrication, BEOL processing on CMOS die or wafers, wire bonding and packaging. Device electrical characterization possible over a frequency range of DC – 40 GHz, a temperature range of 4.2 K to 400 K, an optical excitation range of 190 nm to 1000 nm, and applied magnetic field from 0 to 5000 G. Please contact us for more information.

Knowm BEOL Service

MSS Model

NOTE: If you would like to use this model and/or further develop it, please feel free to do so. First appearance article source: AHaH Computing–From Metastable Switches to Attractors to Machine Learning, Nugent MA, Molter TW (2014) AHaH Computing–From Metastable Switches to Attractors to Machine Learning. PLoS ONE 9(2): e85175. doi: 10.1371/journal.pone.0085175

Many memristive materials have recently been reported, and the trend continues. Memristor models are also being developed and incrementally improved upon. Our generalized metastable switch (MSS) memristor model is an accurate model that captures the behavior of memristors at a level of abstraction sufficient to enable efficient circuit simulations while simultaneously describing a wide a range of possible devices [11]. A MSS is an idealized two-state element that switches probabilistically between its two states as a function of applied voltage bias and temperature. A memristor is modeled by a collection of MSSs evolving in time, which captures the memory-enabling hysteresis behavior. In our semi-empirical model, the total current through the device comes from both a memory-dependent (MSS) current component, $I_{\rm m}$ , and a Schottky diode current, $I_{\rm s}$ in parallel:

$I=\phi I_{\rm m}(V,t)+(1-\phi)I_{\rm s}(V)$

, where $\phi\in{[0,1]}$ . A value of $\phi=1$ represents a device that contains no Schottky diode effects. The Schottky diode effect accounts for the exponential behavior found in many devices and allows for the accurate modeling of that effect, which the MSS component cannot capture alone. The MSS model can be made more complex to account for failure modes, for example by making the MSS state potentials temporally variable. Multiple MSS models with different state potentials can be combined in parallel or series to model increasingly more complex state systems.

Why Another Memristor Model?

Frankly, existing memristor models weren’t all that great for the type of devices we are interested in using to build Thermodynamic-RAM, a neuromorphic co-processor based on the principles of AHaH Computing. We also were faced with the problem that most memristors we have seen display some measure of stochastic behavior, and many model assume a deterministic device. We felt that a stochastic model was a more natural fit to actual device properties. An effective memristive device model for our use case should satisfy several requirements. It should accurately model the device behavior, it should be computationally efficient, and it should model as many different devices as possible.

By adjusting the free variables in the generalized memristive device model and comparing the subsequent current-voltage hysteresis loops to four real world memristive device I–V data, matching model parameters were determined as shown in Table 1. The devices include the Knowm Ag-chalcogenide, $Ag_5In_5Sb_{60}Te_{30}$, $Ge_2Sb_2Te_5$, and $WO_x$ devices, and they represent a wide spectrum of incremental memristive devices found in recent publications exhibiting diverse characteristics.

General memristive device model parameters fit to various devices. The devices used to test our general memristive device model include the Knowm Ag-chalcogenide 1 and 2, $Ag_5In_5Sb_{60}Te_{30}$, $Ge_2Sb_2Te_5$, and $WO_x$ devices. The parameters in this table were determined by comparing the model response to a simulated sinusoidal or triangle-wave voltage to real I–V data of physical devices.

Device $t_{\rm c}$ [ms] $G_{\rm A}$ [mS] $G_{\rm B}$ [mS] $V_{\rm A}$ [V] $V_{\rm B}$ [V] $\phi$ $\alpha_{\rm f}$ $\beta_{\rm f}$ $\alpha_{\rm r}$ $\beta_{\rm r}$
Knowm 1 0.06 3.0 0.01 0.40 0.30 1
Knowm 2 0.1 1.125 0.67 0.27 0.37 1
$Ag_5In_5Sb_{60}Te_{30}$ 0.15 40 10 .23 .25 1
$Ge_2Sb_2Te_5$ 0.42 .12 1.2 .9 0.6 0.7 $5\times 10^{-3}$ 3.0 $5\times 10^{-3}$ 3.0
$WO_x$ 0.80 .025 0.004 0.8 1.0 .55 $1\times 10^{-9}$ .85 $22\times 10^{-9}$ 6.2

Knowm Memristor Model Fit

The Model in Action

The model can be used in basic circuit simulations as shown in the following table.

Knowm Memristor Model Circuit Simulation

The AHaH rule naturally forms decision boundaries that maximize the margin between data distributions. Weight space plots show the initial weight coordinate (green circle), the final weight coordinate (red circle) and the path between (blue line). Evolution of weights from a random normal initialization to attractor basins can be clearly seen for the circuit model.

Knowm Memristor Model Neuromorphic Simulation

Generalized Metastable Switch Memristive Device Model

In our proposed semi-empirical model, the total current through the device comes from both a memory-dependent current component, $I_{\rm m}$, and a Schottky diode current, $I_{\rm s}$ in parallel:

$I=\phi I_{\rm m}(V,t)+(1-\phi)I_{\rm s}(V)$

, where $\phi\in{[0,1]}$. A value of $\phi=1$ represents a device that contains no Schottky diode effects. The Schottky component, $I_{\rm s}(V)$, follows from the fact that many memristive devices contain a Schottky barrier formed at a metal–semiconductor junction. The Schottky component is modeled by forward bias and reverse bias components as follows:

$I_{\rm s}=\alpha_{\rm f}e^{\beta_{\rm f}V}-\alpha_{\rm r}e^{-\beta_{\rm r}V}$

, where $\alpha_{\rm f}$, $\beta_{\rm f}$, $\alpha_{\rm r}$, and $\beta_{\rm r}$ are positive valued parameters setting the exponential behavior of the forward and reverse biases exponential current flow across the Schottky barrier.

Knowm Generalized Memristor Model

The memory component of our model, $I_{\rm m}$, arises from the notion that memristors can be represented as a collection of conducting channels that switch between states of differing resistance. The channels could be formed from molecular switches, atoms, ions, nanoparticles or more complex composite structures. Modification of device resistance is attained through the application of an external voltage gradient that causes the channels to transition between conducting and non-conducting states. As the number of channels increases, the memristor will become more incremental as it acquires the ability to access more states. By modifying the number of channels we may cover a range of devices from binary to incremental. We treat each channel as a metastable switch (MSS) and the conductance of a collection of metastable switches capture the memory effect of the memristor. An MSS possesses two states, $A$ and $B$, separated by a potential energy barrier as shown below.

Meta-stable Switches

Let the barrier potential be the reference potential $V = 0$. The probability that a single MSS will transition from the B state to the A state is given by $P_{\rm A}$, while the probability that the MSS will transition from the $A$ state to the $B$ state is given by $P_{\rm B}$. The transition probabilities are modeled as:

$P_{\rm A} = \alpha \frac{1}{{1 + {e^{ \beta \left( {V - {V_{\rm A}}} \right)}}}} = \alpha \Gamma \left( { V,{V_{\rm A}}} \right)$

and

$P_{\rm B} = \alpha \left( {1 - \Gamma \left( {V, -{V_{\rm B}}} \right)} \right)$

, where $\beta = \frac{q}{{kT}} = {({V_{\rm T}})^{ -1}}$. Here, $V_{\rm T}$ is the thermal voltage and is equal to approximately $26~{\text{m}}{{\text{V}}^{ -1}}$ at $T=300~K$, $\alpha = \frac{{\Delta t}}{{{t_{\rm c}}}}$ is the ratio of the time step period $\Delta t$ to the characteristic time scale of the device, $t_{\rm c}$, and $V$ is the voltage across the switch. The probability ${P_{\rm A}}$ is defined as the positive-going direction, so that a positive applied voltage increases the chances of occupying the A state. An MSS possesses utility in an electrical circuit as an adaptive element so long as these conductances differ. Each state has an intrinsic electrical conductance given by $G_{\rm A}$ and $G_{\rm B}$. The convention is that $G_{\rm B} > G_{\rm A}$. Note that the logistic function $\frac{1}{{1 + {e^{-x}}}}$ is similar to the hyperbolic-sign function used in other memristive device models including the nonlinear ion-drift, the Simmons tunnel barrier, the threshold adaptive models, and physics-based models. Our use of the logistic function follows simply from the requirement that probabilities must be bounded between 0 and 1.

Logistic Fundtion

It’s worth reiterating at this point that the logistics function gives the probability between 0 and 1 of a MSS switching states and is dependent on the instantaneous voltage, $V$, the time step, $\Delta t$, of the simulation and the temperature, $T$, of the device.

Up until this point we have only considered a single MSS being in the $A$ or $B$ state and its probability of it changing states given external stimuli. We now model a memristor as a collection of $N$ MSSs evolving in discrete time steps, $\Delta t$. The total memristor conductance is given by the sum over each MSS:

${G_{\rm m}} = {N_{\rm A}}{G_{\rm A}} + {N_{\rm B}}{G_{\rm B}} = {N_{\rm B}}\left( {{G_{\rm B}} - {G_{\rm A}}} \right) + N{G_{\rm A}}$

, where $N = N_{\rm A} + N_{\rm B}$, $N_{\rm A}$ is the number of MSSs in the A state, $N_{\rm B}$ is the number of MSSs in the $B$ state and $G_{\rm A} , G_{\rm B}$ are the intrinsic conductances of the MSSs respectively. At each time step some subpopulation of the MSSs in the $A$ state will transition to the $B$ state, while some subpopulation in the B state will transition to the A state. Intuitively, a MSS is most likely to switch its state when the electrical field applied across it is near and above it’s switching thresholds $V_{\rm A}$ and $V_{\rm B}$. Since all $N$ MSSs are acting in parallel to model the entire memristor, it’s this combined population state that determine the device’s overall conductance at any given point in time. The memristor’s memory state is thus the collection of the individual states of all the MSSs. Since the model keeps track of the state that each MSS is in, it can easily determine the entire device’s conductance by a sum of products. The current through the device is thus the instantaneous voltage times the conductance, a.k.a Ohm’s Law.

The probability that $k$ MSSs will transition out of a population of $n$ MSSs is given by the binomial distribution:

$B\left( {k,n,p} \right) = \frac{{n!}}{{k!\left( {n-1} \right)!}}{p^k}{\left( {1 p} \right)^{n k}}$

, where $p$ is the probability a MSS will transition states given above by $P_{\rm A}$ and $P_{\rm B}$. As $n$ becomes large we may approximate the binomial distribution with a normal distribution:

$\mathcal{N}\left( {\mu ,{\sigma ^2}} \right) = \frac{{{e^{\frac{{ {{\left( {x \mu } \right)}^2}}}{{2{\sigma ^2}}}}}}}{{\sqrt {2\pi {\sigma ^2}} }}$

, where $\mu = np$ and ${\sigma ^2} = np\left( {1 - p} \right)$. Therefore at each time step we have two normal distributions defined by $N_{\rm A}$, $N_{\rm B}$, $P_{\rm A}$ and $P_{\rm B}$, which is a function of instantaneous voltage, $V$, the time step, $\Delta t$, of the simulation and the temperature, $T$, of the device. These two distributions can be sampled to get a random number of MSSs switching their states. Because the normal distribution is continuous, we round it to the nearest discrete value.

The total change in the number of MMSs in the $B$ state is modeled as a probabilistic process where the number of switches that transition between A and B states and vice versa is picked from two normal distributions with a center at $np$ and variance $np(1 - p)$, and where the state transition probabilities are given above. The change in the number of MMSs in the $B$ state is given by the contribution from two random variables picked from two normal distributions:

$\Delta {N_{\rm B}} = {N_{\rm A \rightarrow B}} - {N_{\rm B \rightarrow A}} = \mathcal{N}_A\left( {{N_{\rm A}}{P_{\rm A}},{N_{\rm A}}{P_{\rm A}}\left( {1 -{P_{\rm A}}} \right)} \right) - \mathcal{N}_B\left( {{N_{\rm B}}{P_{\rm B}},{N_{\rm B}}{P_{\rm B}}\left( {1 -{P_{\rm B}}} \right)} \right)$

, where ${N_{\rm A \rightarrow B}}$ and ${N_{\rm B \rightarrow A}}$ are the number of switches transitioning from the $A$ state to the $B$ state and vice versa. At each time step, we are calculating the state of the memristor given by the number of meta stable switches in the \(B[/latex] state, which was a function of the instantaneous voltage and the time step since the last simulated update.

The change in the memristor conductance is thus given by:

$\Delta G_m = {\Delta N_{\rm B}} ({G_{\rm B}} - {G_{\rm A}})$

, and the memory-dependent current is thus:

$I_{\rm m}= V \left(G_m + \Delta G_m \right)$

, where $V$ is the voltage across the memristor during the time-step.

Reducing the number of MSSs in the model will reduce the averaging effects and cause the memristor to behave in a more stochastic way. Note that as the number of MSSs becomes small, the normal approximation to the binomial distribution also breaks down. In this case, one could use the binomial distribution directly if so desired.

Model Conclusion

The generalized metastable switch memristor model presented above does an excellent job at modeling the behavior of a wide range of devices (Knowm Ag-chalcogenide, $Ag_5In_5Sb_{60}Te_{30}$, $Ge_2Sb_2Te_5$, and $WO_x$) under a diverse set of simulation conditions: sinusoidal and triangle drive waveforms, pulses, positive and negative voltages, and two devices connected in series. The total current through the device comes from both a memory-dependent (MSS) current component, $I_{\rm m}$, and a Schottky diode current, $I_{\rm s}$ in parallel, which allows for concisely and intuitively capturing both the memory-dependent hysteresis and Schottky diode current behavior of a diverse set of devices. Furthermore, the model is computationally efficient and has served well in accurately describing device behavior and forming the basis for memristor-based neuromorphic hardware circuit simulations.

The above introduction is a modified excerpt from our 2014 PLoS One paper. To learn more about the theory of AHaH computing and how memristive+CMOS circuits can be turned into self-learning computer architecture using AHaH plasticity, download the paper at: AHaH Computing–From Metastable Switches to Attractors to Machine Learning.

AHaH Computing

Machine learning (ML) systems are composed of (usually large) numbers of adaptive weights. The goal of ML is to adapt the values of these weights based on exposure to data to optimize a function. This foundational objective of ML creates friction with modern methods of computing because every adaptation event must reduce to a communication procedure between memory and processing separated by a distance. The power required to simulate adaptive weights grows impractically large as the number of weights increases owing to the tremendous energy consumed shuttling information back and forth. This is commonly knowm as the von Neumann Bottleneck and leads to what we call the The Adaptive Power Problem.

If current computing methods give us the (remarkable) ability to simulate any possible interaction or “adaptation”, why pursue any other method of computing? The answer is simple: Energy. Nature does not separate memory and processing. Rather, the act of memory access is the act of computing is the act of learning. As the memory processing distance goes to zero, as the case in Nature and proposed neuromemristive architectures, the power efficiency improves by orders of magnitude compared to von Neumann computers. If we want ML systems that are as powerful and efficient as Nature’s examples, then we must create a new type of hardware that is intrinsically adaptive. One could think of it as “Soft-Hardware”.

Neurobiological research has unearthed dozens of plasticity methods, and they all appear to be important to brain function. The more one digs into the literature, the more complex and confusing it becomes. How do we choose a method, or combination of methods, to include in our soft-hardware? It is often said that problems cannot be solved at the same level of thinking that created them. When we step back a level from the brain and we look at all of Nature, we find a viable solution. It is all around us in both biological and non-biological form.The solution is simple, ubiquitous, and it is provably universal.

We find it in rivers, trees, lighting and fungus, but we also find it deep within us. The air that we breath is coupled to our blood through thousands of bifurcating flow channels that form our lungs. Our brain is coupled to our blood through thousands of bifurcating flow channels that form our circulatory system. The neurons in our brains are coupled to each other through thousands of bifurcating flow channels that form our axons and dendrites. Notice a pattern? It is in rivers, lightening, plants, mycelium networks, and even multi-cellular bacteria.

Memristive Synapse

At all scales of organization we see the same patterns built from the same building block. All of these processes are fundamentally related and can be described as free energy dissipating through adaptive containers or, more generally, as energy dissipation pathways competing for conducting resources. We call this mechanism or process Anti-Hebbian and Hebbian (AHaH) plasticity. It is computationally universal, but perhaps more importantly, it leads to general-purpose solutions in machine learning.

In the open-access peer-reviewed paper titled AHaH Computing–From Metastable Switches to Attractors to Machine Learning we detailed how the attractor points of a plasticity rule we call Anti-Hebbian and Hebbian (AHaH) plasticity are computationally complete logic functions as well as building blocks for machine learning functions. We further demonstrate that AHaH plasticity can be attained from simple memristive circuitry attempting to maximize circuit power dissipation in accordance with ideas in non-equilibrium Thermodynamics. Our goal is to lay a foundation for a new type of practical computing based on the configuration and repair of volatile switching elements. We have traversed a large gap from volatile memristive devices to demonstrations of computational universality and machine learning. In short, it has been demonstrated that:

1. AHaH plasticity emerges from the interaction of volatile competing energy dissipating pathways.
2. AHaH plasticity leads to attractor states that can be used for universal computation and advanced machine learning
3. Neural nodes operating AHaH plasticity can be constructed from simple memristive circuits.

For more in-depth information about AHaH Computing, Thermodynamic RAM and the Knowm Tech Stack, make sure to check out knowm.org/technology and knowm.org/learn!

Happy Memristing!

If you have any questions, please don’t hesitate to contact us via email at contact@knowm.org!