If you are new to memristors we recommend purchasing our Memristor Discovery Kit. The included 60 page user manual will guide you safely through a number of experiments without hurting the memristors or yourself.

Memristor Discovery Manual Front

Memristor Discovery Manual Front

Where can I get more technical information?

Please download the data sheet from here:


Where can I find a mathematical model?

While there is not yet a definitive mathematical model for our (or any) memristor, we maintain a public repository of models here:


In most cases the best model has as much to do with the desired simulation tools and limitation thereof as it does with accurate memristor models. Our stance is “it’s better to experiment with real memristors than simulate circuits with models derived from cherry-picked data”. So our answer in many cases is “test them yourself”.

In the datasheet, you state that the maximum current is 1 mA for W and 0.05 mA for C devices. However, later on you show V/I curves up to several mA (is the unit A, so 0.008 = 8 mA?) in Fig. 7. How should we reconcile this information?

Our memristors will still work at higher currents, but there is an irreversible lowering of the HRS (see data sheet) and they will have reduced switching lifetime. On the plus side increase current is better in some situations for example to minimize effect of circuit parasitics. If you are OK with this, then you can operate at higher currents.

For much higher current spikes the temperature increase can cause a melting of the chalcogenide glass which will result in random changes in device properties when it freezes again and the glass network changes. There is no hard defined limit, just an increasing chance that the memristor will change properties and start acting strange. Since the devices typically do not just ‘stop working’ at higher currents but undergo random changes, it can get very confusing and frustrating. In general it’s best to use the lowest current and voltage that will reliably drive the memristor within whatever circuit you are using.

Our device is not exactly matching your default MSS model very well. Why?

Our Generalized MSS model was not developed specifically for our memristors. It is a general model for all memristors and its parameters can be adjusted. Ron and Roff will absolutely need to be adjusted for your specific circuit, and other parameters may have to be adjusted as well. Ron and Roff values are a function of your driving circuit (compliance or limiting series resistance) and history of use (if you operated it at elevated currents in the past). Given those conditions you must adjust a models parameters to fit your particular circuit conditions.

Is it valid to consider the W-SDC device under the class of ion conducting electrolyte chalcogenide resistive switching cell?

Not given the limiting definition of the ‘ion conducting electrolyte chalcogenide’ type of resistive switching cell. We prefer to classify our memristors as a self-directed channel ion conducting/phase-change mixture.

Is the resistance switching in the (-0.5V, 0.5V) pulsing regime or sinusoidal voltage sweep regime due to the Ag+ conductive bridge formation, only, or should we expect at least any partial crystallization or amorphization as in the Ge2Sb2Te5 phase change memory (PCM) cells?

It’s incorrect to discuss this device as forming an ‘Ag+ conductive bridge’. The device will conduct due to a mixture of phase change crystalline regions, and Ag within the permanent chemically altered pathway. The phrase ‘conductive bridge’ refers to those device types that use Ag for form conductive pathways randomly through an amorphous material to lower the resistance and to dissolve those pathways in order to increase resistance. This is not the case with an SDC device which forms a permanently chemically altered pathway that Ag ions can be displaced into and move around within in order to change the resistance continuously.

Are the same switching dynamics (threshold switching, Pool Frenkel conduction) which are dominant for PCM cells also valid for your Ag-Chalcogenide device? Or should we only consider the Ag+ conductive filament conductance?

Conduction in amorphous systems is complicated. All possibilities need to be investigated when making a determination for a particular system. For the SDC system (not the Knowm W-SDC system as that is still under investigation), the typical mechanisms are all contributors, including Mott’s variable range hopping, direct tunneling, FN, PF, extended state, Schottky.

Phase change memories have a typical negative differential resistance (NDR) during the reset-set transition when a threshold current has been reached. The W-SDC device also has a similar behavior near -0.35V during set-reset transition. Your colleagues and you have mentioned this region which we also occasionally observe experimentally in “Silver Chalcogenide Based Memristor Devices” paper, and “Compact Method for Modeling and Simulation of Memristor Devices” paper. The problem is that in the I-V curves recorded from the device, the NDR region has not always been observed. Is it possible to DC drive the memristive device to this NDR region and stay there or is it just due to the threshold switching in the device?

Be careful not to mix up device types. The papers you mention are not for the W-SDC device that you are measuring and will definitely exhibit behaviors that are not observable or different for the W-SDC. There are two NDR regions that can be observed to various degrees in different device types. One marks the transition from Low R state to High R state. The other is observable (under certain circumstances) in the direction of applied voltage that induces a Low R state. On which side is the NDR you’re referring to?

Additionally, the device SPICE model provided in your papers mentioned above, shows a hard switching behavior during the DC I-V characterization (actually this is what we expect as the driving sinusoidal signal is slower that the time constant of the device so a saturation occurs in either of the resistive states), so we also cannot observe the NDR region in DC I-V simulations.

The spice simulations in those papers are for different device types.

One of your tutorials sais that the memristor can be formed by increasing the amplitude of an applied sine wave to 1Vp (https://www.youtube.com/watch?v=rfKtKxp5CW8). However another tutorial formed the device by applying a 1Vp sine wave and changed the DC offset from +/-0.5V (https://www.youtube.com/watch?v=rxAcqBD_xz8). Is one forming procedure better than the other?

We have not yet noticed a difference. Any low-frequency voltage cycling of the device that triggers a memristive response appears to be sufficient, however we are not aware of any specific studies looking at performance attributes as a function of initial device forming.